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tm 74ac109, 74act109 dual jk positive edge-triggered flip-flop march 2007 ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 74ac109, 74act109 dual jk positive edge-triggered flip-flop features i cc reduced by 50% outputs source/sink 24ma act109 has ttl-compatible inputs general description the ac/act109 consists of two high-speed completely independent transition clocked jk flip-flops. the clocking operation is independent of rise and fall times of the clock waveform. the jk design allows operation as a d-type flip-flop (refer to ac/act74 data sheet) by connecting the j and k inputs together. asynchronous inputs: low input to s d (set) sets q to high level low input to c d (clear) sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. connection diagram pin descriptions order number package number package description 74ac109sc m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ac109sj m16d 16-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac109mtc mtc16 16-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act109sc m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ac109mtc mtc16 16-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act109pc n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pin names description j 1 , j 2 , k 1 , k 2 data inputs cp 1 , cp 2 clock pulse inputs c d1 , c d2 direct clear inputs s d1 , s d2 direct set inputs q 1 , q 2 , q 1 , q 2 outputs fact is a trademark of fairchild semiconductor corporation .
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 2 logic symbols truth table each half. h = high voltage level l = low voltage level = low-to-high transition x = immaterial q 0 (q 0 ) = previous q 0 (q 0 ) before low-to-high transition of clock logic diagram one half shown. please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. inputs outputs s d c d cp j k q q lhxxxhl hlxxxlh llxxxhh hh lllh hh hl t oggle hh lhq 0 q 0 hh hhhl hhlxxq 0 q 0 ieee/iec
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 3 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?.5v to +7.0v i ik dc input diode current v i = ?.5v v i = v cc + 0.5v ?0ma +20ma v i dc input voltage ?.5v to v cc + 0.5v i ok dc output diode current v o = ?.5v v o = v cc + 0.5v ?0ma +20ma v o dc output voltage ?.5v to v cc + 0.5v i o dc output source or sink current ?0ma i cc or i gnd dc v cc or ground current per output pin ?0ma t stg storage temperature ?5? to +150? t j j unction temperature 140? symbol parameter rating v cc supply voltage ac act 2.0v to 6.0v 4.5v to 5.5v v i input voltage 0v to v cc v o output voltage 0v to v cc t a operating temperature ?0? to +85? ? v / ? t minimum input edge rate, ac devices: v in from 30% to 70% of v cc , v cc @ 3.3v, 4.5v, 5.5v 125mv/ns ? v / ? t minimum input edge rate, act devices: v in from 0.8v to 2.0v, v cc @ 4.5v, 5.5v 125mv/ns
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 4 dc electrical characteristics for ac notes: 1. all outputs loaded; thresholds on input associated with output under test. 2. maximum test duration 2.0ms, one output loaded at a time. 3. i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 2.1 2.1 v 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 0.9 0.9 v 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 i out = ?0? 2.99 2.9 2.9 v 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 v in = v il or v ih : 3.0 i oh = ?2ma 2.56 2.46 4.5 i oh = ?4ma 3.86 3.76 5.5 i oh = ?4ma (1) 4.86 4.76 v ol maximum low level output voltage 3.0 i out = 50? 0.002 0.1 0.1 v 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 v in = v il or v ih : 3.0 i ol = 12ma 0.36 0.44 4.5 i ol = 24ma 0.36 0.44 5.5 i ol = 24ma (1) 0.36 0.44 i in (3) maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?.0 ? i old minimum dynamic output current (2) 5.5 v old = 1.65v max. 75 ma i ohd v ohd = 3.85v min. ?5 ma i cc (3) maximum quiescent supply current 5.5 v in = v cc or gnd 2.0 20.0 ?
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 5 dc electrical characteristics for act notes: 4. all outputs loaded; thresholds on input associated with output under test. 5. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 2.0 2.0 v 5.5 1.5 2.0 2.0 v il maximum low level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 0.8 0.8 v 5.5 1.5 0.8 0.8 v oh minimum high level output v oltage 4.5 i out = ?0? 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v in = v il or v ih : 4.5 i oh = ?4ma 3.86 3.76 5.5 i oh = ?4ma (4) 4.86 4.76 v ol maximum low level output v oltage 4.5 i out = 50? 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v in = v il or v ih : 4.5 i ol = 24ma 0.36 0.44 5.5 i ol = 24ma (4) 0.36 0.44 i in maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?1.0 ? i cct maximum i cc /input 5.5 v i = v cc ?2.1v 0.6 1.5 ma i old minimum dynamic output current (5) 5.5 v old = 1.65v max. 75 ma i ohd v ohd = 3.85v min. ?5 ma i cc maximum quiescent supply current 5.5 v in = v cc or gnd 2.0 20.0 ?
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 6 ac electrical characteristics for ac note: 6. voltage range 3.3 is 3.3v ?0.3v. voltage range 5.0 is 5.0v ?0.5v. ac operating requirements for ac note: 7. voltage range 3.3 is 3.3v ?0.3v. voltage range 5.0 is 5.0v ?0.5v symbol parameter v cc (v) (6) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. f max maximum clock frequency 3.3 125 150 100 mhz 5.0 150 175 125 t plh propagation delay, cp n to q n or q n 3.3 4.0 8.0 13.5 3.5 16.0 ns 5.0 2.5 6.0 10.0 2.0 10.5 t phl propagation delay, cp n to q n or q n 3.3 3.0 8.0 14.0 3.0 14.5 ns 5.0 2.0 6.0 10.0 1.5 10.5 t plh propagation delay, c dn or s dn to q n or q n 3.3 3.0 8.0 12.0 2.5 13.0 ns 5.0 2.5 6.0 9.0 2.0 10.0 t phl propagation delay, c dn or s dn to q n or q n 3.3 3.0 10.0 12.0 3.0 13.5 ns 5.0 2.0 7.5 9.5 2.0 10.5 symbol parameter v cc (v) (7) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50 pf units t yp. guaranteed minimum t s setup time, high or low, j n or k n to cp n 3.3 3.5 6.5 7.5 ns 5.0 2.0 4.5 5.0 t h hold time, high or low, j n or k n to cp n 3.3 ?.5 0 0 ns 5.0 ?.5 0.5 0.5 t w pulse width, c dn or s dn 3.3 2.0 7.0 7.5 ns 5.0 2.0 4.5 5.0 t rec recovery time, c dn or s dn to cp n 3.3 ?.5 0 0 ns 5.0 ?.5 0 0
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 7 ac electrical characteristics for act note: 8. voltage range 5.0 is 5.0v ?0.5v ac operating requirements for act note: 9. voltage range 5.0 is 5.0v ?0.5v capacitance symbol parameter v cc (v) (8) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. f max maximum clock frequency 5.0 145 210 125 mhz t plh propagation delay, cp n to q n or q n 5.0 4.0 7.0 11.0 3.5 13.0 ns t phl propagation delay, cp n to q n or q n 5.0 3.0 6.0 10.0 2.5 11.5 ns t plh propagation delay, c dn or s dn to q n or q n 5.0 2.5 5.5 9.5 2.0 10.5 ns t phl propagation delay 5.0 2.5 6.0 10.0 2.0 11.5 ns c dn or s dn to q n or q n symbol parameter v cc (v) (9) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units t yp. guaranteed minimum t s setup time, high or low, j n or k n to cp n 5.0 0.5 2.0 2.5 ns t h hold time, high or low, j n or k n to cp n 5.0 0 2.0 2.0 ns t w pulse width, cp n or c dn or s dn 5.0 3.0 5.0 6.0 ns t rec recovery time, c dn or s dn to cp n 5.0 ?.5 0 0 ns symbol parameter conditions typ. units c in input capacitance v cc = open 4.5 pf c pd po w er dissipation capacitance v cc = 5.0v 35.0 pf
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 8 physical dimensions dimensions are in millimeters unless otherwise noted. figure 1. 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow pa ck ag e number m16a
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 9 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 2. 16-lead small outline package (sop), eiaj type ii, 5.3mm wide pa ck ag e number m16d
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 10 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 3. 16-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa ck ag e number mtc16 0.65 4.40.1 mtc16rev4 0.11 4.55 5.00 5.000.10 12 7.35 4.45 1.45 5.90
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 11 physical dimensions (continued) dimensions are in inches (millimeters) unless otherwise noted. figure 4. 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pa ck ag e number n16e
74ac109, 74act109 dual jk positive edge-triggered flip-flop ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac109, 74act109 rev. 1.5 12 tradem a rks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intend ed to be an exhaustive list of all such trademarks. acex across the board. around the world. activearray bottomless build it now coolfet crossvolt ctl current transfer logic dome e 2 cmos ecospark ensigna fact quiet series fact fast fastr fps frfet globaloptoisolator gto hisec i-lo implieddisconnect intellimax isoplanar microcoupler micropak microwire msx msxpro ocx ocxpro optologic optoplanar pacman pop power220 power247 poweredge powersaver powertrench programmable active droop qfet qs qt optoelectronics quiet series rapidconfigure rapidconnect scalarpump smart start spm stealth superfet supersot -3 supersot -6 supersot -8 syncfet tcm the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinywire trutranslation p serdes uhc unifet vcx wire disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ich, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. re v. i24

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